1. Field of the Invention
The invention relates generally to storage controllers and storage network switching components and more specifically to methods and structures for debugging Double Data Rate (“DDR”) memory thereof.
2. Discussion of Related Art
Modern computer processing hosts a relatively large number of complex applications using ever increasingly high data rates. The processors involved are generally configured with high-speed memory devices, such as double-data rate (DDR) synchronous dynamic random access memory (SDRAM). The DDR SDRAM is approximately twice as fast as a single data rate SDRAM running at the same clock speed because a DDR SDRAM transfers data on both the rising and falling edge of a differential clock provided by a DDR controller.
The higher data rate speeds of DDR memory may present issues regarding the timing of data transfers. Since data is transferred at both the rising edge and falling edge of the clock input, timing requirements of a DDR memory oftentimes demand a more precise synchronization for both data write and read operations. Synchronization problems may result in errors while reading data from memory and writing data to memory. Generally, a DDR controller generates internal clock pulses for synchronizing data write operations and read operations. For example, clock and/or control signals may become desynchronized due to physical characteristics of the devices mounted on the board and changes in the environment in which the memory is operating. Examples of the environmental conditions include voltage and temperature changes may cause drift from an optimal operating point of the DDR memory.
Because of the higher speeds at which DDR memory operates, the memory functions with a narrow valid data window or “eye” in which data is processed. Failure to properly read or write data within this data window results in errors being generated within the system. Other factors such as jitter and skew due to mismatched board trace lengths may also give rise to errors. Accordingly, the DDR memory is typically initialized via firmware to establish synchronization for the DDR and a device with which the memory is configured.
Storage controllers and switching components in the data storage industry are examples of devices that employ DDR memory due to their ever increasing speeds and the desire for faster performance The increasing speed of DDR memory, however, has made debugging of the DDR memory interface increasingly important. For example, end users of the storage controllers often create their own means for initializing the DDR memory. Such is generally done via the introduction of proprietary firmware being implemented by the end user in the storage controller after delivery of the storage controller from the manufacturer. This implementation of proprietary DDR initialization introduces new debugging challenges to the storage controller manufacturers that are required to fix delivered storage controllers when problems arise. To counter this, manufacturers created initialization modules for the DDR memory of the storage controller. These DDR initialization modules have a pre-defined application programming interface (API) that end users would integrate into their existing firmware. While this provided a more reliable method for initializing the DDR memory, a manufacture still relied on an end user properly integrating the DDR initialization module to ensure that the interface functioned correctly. Any incorrect implementation would again result in time consuming and costly debugging of the DDR memory.